The present invention relates to a lead frame used for a package including a heatsink, that is used for a device such as a mold-type high-frequency power device, and a semiconductor device using the lead frame.
A conventional semiconductor device being provided with a package including a heatsink is disclosed in, for example, in Japanese Published Unexamined Patent Application No. 130782/1995 (Tokukaihei 7-130782, published on May 19, 1995). Referring to FIGS. 6(a) through 9(b), the following explanation describes the construction thereof.
FIG. 6(a) is a plan view showing a conventional semiconductor device in a forming process. FIG. 6(b) is a sectional view taken along line 6bxe2x80x946b shown in FIG. 6(a). Further, FIG. 7(a) is a sectional view taken along line 7axe2x80x947a shown in FIG. 6(a). FIG. 7(b) is a sectional view taken along line 7bxe2x80x947b shown in FIG. 6(a). The semiconductor device (conventional example 1) is formed by a chip 52 and a package 54 including the chip 52.
The package 54 is constituted by a lead frame 56, bonding wires 58, a heatsink 60, and a sealing member 62. The lead frame 56 is constituted by a die pad 56a and leads 56b and is provided with a chip 52 which is die-bonded via an Ag paste 64 on the die pad 56a. As the chip 52, for example, a GaAsMMIC (Monolithic Microwave Integrated Circuit) chip can be adopted.
The bonding wires 58 is formed by an Au wire and has two kinds of wires of GND wires 58a and lead wires 58b for connecting chip pads 52a, which are formed on the chip 52, and the die pad 56a or the leads 56b, which are formed on the lead frame 56. A GND wiring on a circuit of the chip 52 is formed by the GND wires 58a, and a GND inductance occurs during an operation.
A heatsink 60 is a copper block that is entirely bonded to a back of a surface of the die pad 56a via a conductive paste 66, the surface having the chip 52 disposed thereon. Further, a surface of the heatsink 60, that is entirely bonded to the die pad 56a, has a back surface exposed from a sealing member 62. When the present semiconductor device is packaged, the exposed surface is soldered onto a packaged surface. With this arrangement, it is easier to release heat occurring during an operation of the chip 52, through the heatsink 60 to the outside of a semiconductor package.
The semiconductor device is formed in the following manufacturing process. Firstly, the copper heatsink 60 of 2.0xc3x972.8xc3x970.7 mm, that is separately formed, is entirely bonded via the conductive paste 66 on the back of the copper lead frame 56 having a thickness of 0.15 mm. The Ag paste 64 is applied onto the die pad 56a of the lead frame 56, and the chip 52 is die-bonded.
Afterwards, by the bonding wires 58, the chip pads 52a of the chip 52 are wire-bonded to the die pad 56a or the leads 56b of the lead frame 56. And then, the semiconductor device is transfer molded by the sealing member 62.
Next, FIGS. 8(a) through 9(b) show a conventional semiconductor device (conventional example 2) being provided with another conventional package including a heatsink. FIG. 8(a) is a plan view showing the semiconductor device of the conventional example 2 in a forming process. FIG. 8(b) is a sectional view taken along line 8bxe2x80x948b shown in FIG. 8(a). And FIG. 9(a) is a sectional view taken along line 9axe2x80x949a shown in FIG. 8(a). FIG. 9(b) is a sectional view taken along line 9bxe2x80x949b shown in FIG. 8(a). Here, those members that have the same functions and that are described in conventional example 1 are indicated by the same reference numerals and the description thereof is omitted.
Here, conventional example 2 is different from conventional example 1 as follows: in conventional example 2, a lead frame 56 of a semiconductor device does not include a die pad 56a (see FIG. 6(a)), and a heatsink 60 also serves as a die pad. Further, in the lead frame 56, lower surfaces of all leads 56b are mounted on the upper surface of the heatsink 60 via an insulating paste 68. Moreover, GND wires 58a are bonded onto the upper surface of the heatsink 60 and form a GND wiring on a circuit of a chip 52, so that a GND inductance occurs during an operation.
The semiconductor device of conventional example 2 is formed in the following manufacturing process. Firstly, a Ag paste 64 is applied to the center of the surface of the heatsink 60 that has the chip 52 mounted thereon, and the chip 52 is die-bonded. And then, the heatsink 60 and the lead frame 56 are disposed with the insulating paste 68. Afterwards, the chip pads 52a are wire-bonded to the leads 56b or the upper surface of the heatsink 60 also serving as the die pad 56a. And then, the semiconductor device is completed after performing the same process as conventional example 1.
Incidentally, when the semiconductor device, particularly a high-frequency power device is packaged into a resin mold, a heat-releasing property and a high-frequency property are important. Namely, in view of releasing heat, the chip 52 has a large amount of self-heating, so that it is necessary to reduce and simplify (reduce heat resistance) a heating path and to release generated heat efficiently to the outside so as to restrict a higher temperature in the chip 52. Moreover, in view of the high-frequency property, a GND inductance needs to be minimized.
However, a package 54 used for a semiconductor device of the conventional art has the following problem regarding a heat-releasing path and a GND inductance.
Firstly, in conventional example 1, on the heat-releasing path, many members are disposed between the chip 52 serving as a heat-releasing part and the outside of the semiconductor device. The heat-releasing path has an extremely large heat resistance of, for example, 50xc2x0 C./W.
FIG. 10 shows the heat-releasing path under such a condition for each heat resistance (simple resistance). FIG. 10 is a conceptual drawing showing the heat-releasing path of conventional example 1. To be specific, the heat-releasing path is: a heat-releasing part of the chip 52xe2x86x92a base member of the chip 52 (R1)xe2x86x92the Ag paste 64 (R2)xe2x86x92die pad 56a (R3)xe2x86x92a conductive paste 66 (R4)xe2x86x92the heatsink 60 (R5)xe2x86x92the outside of the package 54. This can be cumulatively expressed as follows: package heat resistance: Rth=R1+R2+R3+R4+R5.
As described above, conventional example 1 has a long and complicated heat-releasing path, so that the package heat resistance is high. Thus, when the semiconductor device of conventional example 1 is continuously operated, the temperature may rise too much inside the package 54. When the temperature is too high in the package 54, the following phenomenon appears so as to cause a problem. Firstly, an output power value serving as an electrical property is reduced with time. Further, even when an input power is increased to obtain a desired output power, the output power value is at saturation due to a high temperature of the inside, so that the output power value cannot be raised any more.
In order to solve the problem, it is necessary to shorten and simplify the heat-releasing path to a minimum, to reduce heat resistance of the package 54, and to improve a heat-releasing property so as to prevent an increase in temperature inside the package 54. Hence, conventional example 2 achieves a construction which does not include the die pad 56a so as to realize a heat-releasing path in which R3 and R4 are omitted.
Here, in conventional example 2, the lead frame 56 and the heatsink 60 are mounted on the leads 56b of the lead frame 56. The leads 56b are separated later to form terminals of the semiconductor device, so that the leads 56b need to be electrically insulated. Therefore, a part for mounting the lead frame 56 and the heatsink 60 is generally mounted via the insulating paste 68, an insulating tape, an insulating adhesive, and others. However, this arrangement causes the following problem.
In conventional example 2, the lead frame 56 and the heatsink 60 are firstly disposed, and then, the chip 52, the heatsink 60, and the lead frame 56 are wire-bonded via the bonding wires 58. The heatsink is heated at this time so as to generate gas of organic components from the insulating paste 68 and others.
The generation of gas deteriorates the surfaces of the lead frame 56 and the heatsink 60 so as to increase a possibility of causing a connecting defect of the wire bonding. Thus, the reliability of the wire bonding is reduced and a fraction defective is increased. Further, the heat sink 60 is heated so as to reduce the adhesion of the insulating paste 68 and others, so that the heatsink 60 becomes detached from the lead frame 56.
Furthermore, in conventional example 2, it is necessary to apply the insulating paste 68 and others merely on the surfaces of a large number of the leads 56b disposed in the lead frame 56, the surfaces being connected to the heatsink 60. Thus, the manufacturing cost is further raised due to an increase in the fraction defective as well.
Additionally, there has been a problem of a GND inductance, that appears in the above conventional arts.
In a frequency area of 1 GHz or more, which is applicable to a high-frequency power device, grounding is made by the GND wires 58a, so that a GND inductance occurs.
In view of a circuit of the chip 52, the grounding (GND) on the circuit is raised from an original grounding by the appearing GND inductance. Therefore, the output value of the conductive device is reduced from an originally set output value by a value corresponding to the GND inductance, so that a predetermined output value cannot be obtained.
Therefore, it is necessary to reduce a GND inductance to solve the above problem. In this case, the number of the GND inductance wires 58a can be increased to reduce a GND inductance. However, another problem occurs as follows.
It is necessary to increase the chip pads 52a to dispose a larger number of the GND wires 58a, causing a larger size of the chip. Here, in the case of a chip such as a GaAsMMIC chip serving as the chip 52, a GaAsMMIC wafer serving as a base member is more expensive than Si, so that the cost of the chip 52 is almost determined by the number of the chips 52 mounted on a wafer. Consequently, a larger chip increases the cost of the semiconductor device.
Further, when the pitches of the GND wires 58a are reduced to increase the number of the GND wires 58a, a GND inductance cannot be effectively reduced in a frequency area of 1 GHz or more due to influence of mutual inductance.
As described above, with the conventional lead frame and the semiconductor device using the same, it is difficult to improve a heat-releasing property and a high frequency property without deterioration in reliability and productivity and without increasing the cost accordingly. Hence, the capability of the semiconductor chip cannot be fully exerted.
The present invention is devised to solve the above-mentioned problems. The objective is to provide a lead frame for a semiconductor device that can reduce a heat resistance and improve a heat-releasing property without deterioration in reliability and productivity and accordingly without an increase in cost. Further, the objective is to provide a lead frame for a semiconductor device that can reduce a GND inductance and improve a high-frequency property so as to efficiently exert the capability of a mounted semiconductor chip. Furthermore, the objective is to provide a semiconductor device using such a lead frame used for a semiconductor device.
The lead frame of the present invention is a lead frame used for a semiconductor device. In order to achieve the above objective, the lead frame is provided with an island for mounting a semiconductor chip, a metallic block disposed on the island, and leads extended to the island. In the island, a penetrating hole being larger than the mounted semiconductor chip is formed in an area, in which the semiconductor chip is mounted, and the metallic block is disposed so as to cover the penetrating hole.
According to the above arrangement, the penetrating hole formed in the island of the lead frame is larger than the mounted semiconductor chip, so that the semiconductor chip can be disposed in the penetrating hole. Moreover, the metallic block covers the penetrating hole, so that the semiconductor chip can be disposed on a surface of the metallic block in the penetrating hole, and the metallic block can be used as a heatsink.
Therefore, unlike the conventional art, it is possible to form a heat-releasing path without the necessity for the island disposed between the heatsink and the semiconductor chip serving as a heating part, thereby improving a heat-releasing property.
Moreover, unlike a construction in which the heatsink is mounted on the leads, in the above arrangement, the metallic block serving as the heatsink is disposed on the island of the lead frame. Therefore, it is possible to form a construction in which the leads and the metallic block are insulated from one another without using an insulating paste for mounting the metallic block. Namely, a method can be adopted in which the metallic block is electrically brought into conduction with the island.
Hence, it is possible to prevent a problem such as reduction in adhesion of the heatsink, reduction in reliability of wire-bonding, and more complicated process, that are caused by the insulating paste, which is normally used for a construction in which the heatsink is mounted on the leads.
It is further desirable that the island and the metallic block be formed so as to be separated from the leads in the lead frame.
According to this arrangement, the island and the metallic block are formed so as to be separated from the leads, for example, upon forming the semiconductor device. The island and the metallic block can be electrically insulated from the leads. Therefore, the island can act as a GND on a circuit of the semiconductor chip. When the island acts as the GND, ground terminals of the semiconductor chip can be wire-bonded to the island.
Here, in this arrangement, the semiconductor chip and the island can be disposed on a surface of the metallic block. Thus, as compared with a construction in which the ground terminals are wire-bonded to a surface having the semiconductor chip disposed thereon, it is possible to reduce a height difference between the wire-bonded surfaces. With this arrangement, it is possible to shorten bonding wires so as to reduce a GND inductance on the circuit. As a result, the lead frame having the above construction can improve a high-frequency property.
In order to achieve the above objective, the semiconductor device of the present invention is provided with the lead frame, and the semiconductor chip which is mounted on the metallic block in the penetrating hole formed in the lead frame.
According to the above construction, the metallic block acts as the heatsink, and the semiconductor chip is directly disposed on the heatsink. With this arrangement, it is possible to reduce a heat resistance and to simplify the heat-releasing path, so that heat generated in the semiconductor chip can be released more efficiently.
Consequently, even in the case of a continuous operation of the semiconductor device, it is possible to prevent an increase in temperature of the semiconductor chip therein and reduction in an electrical property such as an output voltage value.
In order to achieve the above objective, the semiconductor device of the present invention is provided with the lead frame, in which the island and the metallic block are formed so as to be separated from the leads, and the semiconductor chip having the ground terminals mounted on the metallic block in the penetrating hole, The ground terminals of the semiconductor chip are connected to the GND wires connected to the island.
According to this arrangement, the semiconductor chip is directly disposed on the metallic block, and the ground terminals of the semiconductor chip are connected to the island of the lead frame via the GND wires. Thus, as compared with a construction in which a surface having the semiconductor chip disposed thereon is connected to the ground terminals, it is possible to reduce a height difference between the connected surfaces because of a thickness of the island. With this arrangement, the GND wires (bonding wires) can be shortened.
Therefore, it is possible to reduce a GND inductance on the circuit of the semiconductor chip as well as to reduce a heat resistance so as to improve a heat-releasing property. As a result, in the present semiconductor device, it is possible to prevent reduction in an output value that is caused by a GND inductance.
In order to achieve the above objective, the semiconductor device of the present invention includes the semiconductor chip having the ground terminals that are mounted on a surface of the heatsink, and a metallic member disposed on the surface of the heatsink that has the semiconductor chip mounted thereon, the ground terminals and the metallic member being wire-bonded to one another.
In the above arrangement, the semiconductor chip is directly disposed on the heatsink, and the ground terminals of the semiconductor chip are connected to the metallic member disposed on the heatsink.
With this arrangement, it is possible to efficiently release heat generated in an operation of the semiconductor chip, via the heatsink to the outside of the semiconductor device. Consequently, it is possible to prevent an increase in temperature of the semiconductor device so as to prevent reduction in an output value, saturation, and other problems that are caused by a higher temperature.
Moreover, the metallic member is disposed on the surface of the heatsink that has the semiconductor chip mounted thereon, so that a height difference can be reduced between an upper surface of the metallic member and the surface of the semiconductor chip that has the ground terminals disposed thereon. This arrangement makes it possible to shorten the bonding wires for grounding of the semiconductor chip. Therefore, it is possible to reduce a GND inductance on the circuit of the semiconductor chip so as to prevent reduction in an output value that is caused by the GND inductance.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.
FIG. 1(a) is a plan view showing a forming process of a semiconductor device in accordance with one embodiment of the present invention. FIG. 1(b) is a sectional view taken along line 1bxe2x80x941b shown in FIG. 1(a).
FIG. 2(a) is a sectional view taken along line 2axe2x80x942a shown in FIG. 1(a). FIG. 2(b) is a sectional view taken along line 2bxe2x80x942b shown in FIG. 1(a).
FIG. 3 is a conceptual drawing showing a heat-releasing path of the semiconductor device of FIGS. 1(a) and 1(b).
FIG. 4 is a conceptual drawing showing an area surrounding GND wires of the semiconductor device shown in FIGS. 1(a) and 1(b).
FIG. 5 is a schematic drawing for comparing GND wire lengths of semiconductor devices shown in one embodiment and a comparative example of the present invention.
FIG. 6(a) is a plan view showing a forming process of a conventional semiconductor device. FIG. 6(b) is a sectional view taken along line 6bxe2x80x946b shown in FIG. 6(a).
FIG. 7(a) is a sectional view taken along line 7axe2x80x947a shown in FIG. 6(a). FIG. 7(b) is a sectional view taken along line 7bxe2x80x947b shown in FIG. 6(a).
FIG. 8(a) is a plan view showing a forming process of another conventional semiconductor device. FIG. 8(b) is a sectional view taken along line 8bxe2x80x948b shown in FIG. 8(a).
FIG. 9(a) is a sectional drawing taken along line 9axe2x80x949a shown in FIG. 8(a). FIG. 9(b) is a sectional drawing taken along line 9bxe2x80x949b shown in FIG. 8(a).
FIG. 10 is a conceptual drawing showing a heat-releasing path of the conventional semiconductor device as a comparative example.
FIG. 11(a) is a schematic drawing showing an area surrounding the GND wires of the conventional semiconductor device. FIG. 11(b) is a schematic drawing showing an area surrounding the GND wires of another conventional semiconductor device as another comparative example.